This invention generally relates to semiconductor devices and methods of fabricating the same and, more specifically, to transistors with surrounded channel regions and methods of fabrication therefor.
As the size of transistors has decreased, short channel effects may extend relatively deep into the devices. In particular, as junction depths have become shallow, leakage current and source/drain resistance have generally increased. In addition, the performance of transistors is closely related with drive currents and the drive current of transistors has generally decreased with reduced channel width.
To address these problems, transistors with various structures have been introduced. In a partially insulated field effect transistor (PiFET), an insulating layer is formed under a channel and has a structure capable of preventing a punch-through phenomenon between source and drain. However, this structure is generally not suitable for a high-performance transistor because the reduction of a drain current due to the reduction of the channel width still remains a problem.
In a conventional gate all around type transistor, a gate surrounds a channel. In such a transistor, a gate electrode is formed in two sides or three sides of a fin-shaped channel, thus increasing the channel length without unduly increasing the planar area of the transistor. A fin field effect transistor (FinFET) having an active region with a fin-shaped extending vertically can reduce the width of a fin needed to form a fully depleted channel. As a result, short channel effect can be reduced. Techniques for fabricating gate all around type transistors are disclosed in Korean Patent Application No. 2001-0019525 entitled “A SEMICONDUCTOR DEVICE HAVING GATE ALL AROUND TYPE TRANSISTOR AND METHOD OF FABRICATING THE SAME” and U.S. Pat. No. 6,605,847 entitled “SEMICONDUCTOR DEVICE HAVING GATE ALL AROUND TYPE TRANSISTOR AND METHOD OF FORMING THE SAME”.
FIGS. 1A to 4A are plan views illustrating a fabricating method of a conventional gate all around type transistor, FIGS. 1B to 4B and 1C to 4C are cross-sectional views of the structures illustrated in FIGS. 1A to 4A in X and Y directions, respectively. Referring to FIGS. 1A, 1B, and 1C, an active layer pattern is formed on a lower substrate 10 and a buried oxide layer 12. The active layer pattern includes a stacked structure including a silicon-germanium layer 14 and a silicon layer 16. A surface of the active layer pattern is oxidized to form an insulating layer 18. Referring to FIGS. 2A, 2B, and 2C, after forming an etch barrier layer on the substrate, the etch barrier layer in a gate region is removed to form an etch barrier pattern 20. A portion of the insulating layer 18 covering the gate region is removed to expose the silicon-germanium layer 14 and the silicon layer 16. The silicon-germanium layer 14 is selectively removed to form a hollow 24 using an isotropic etch process. Because an isotropic etch process is performed to form the hollow 24, the gate region preferable is narrow in exposed width. In order to secure a desired channel length, it is typically required to expose a narrower width than the desired channel length.
Referring to FIGS. 3A, 3B, and 3C, a gate insulating layer 26 is formed on a surface of an exposed silicon layer 16. A conductive layer 28 that fills in the gate region and the hollow is formed. Referring to FIGS. 4A, 4B, and 4C, the conductive layer 28 is removed using an anisotropic etch process or a chemical mechanical polishing (CMP) method to expose the etch barrier pattern 20. The exposed etch barrier layer 20 is removed to expose an active pattern. As shown in FIGS. 4A, 4B, and 4C, a gate electrode 30 is formed on the active pattern. The gate electrode extends along sidewalls of the active pattern and fills in the hollow 24. Accordingly, a channel may be formed at three sides of the active pattern as well as the hollow. Source/drains may be formed at an active region at both sides of the gate electrode.
As shown, a channel length in the hollow is different from that in three sides of the active pattern. As previously mentioned, while selectively etching silicon-germanium, an isotropic etch process is performed in source/drain directions. If the active pattern is thick in the hollow in order to increase a channel width, under-cut will be more pronounced in the source/drain directions. As a result, as the channel width is increased, a width difference of a gate electrode between the hollow and an upper portion of the active pattern is increased.
It is believed that these problems are not recognized in the conventional art. In the event that source/drain are aligned and formed at the gate electrode over the active region, an overlap capacitance between the gate electrode formed at the hollow and source/drain may be increased. As a result, speed of transistors may be limited. In addition, because a part of a gate insulating layer is overlapped with source/drain, reliability may be reduced.